G11CSTATIC STORES semiconductor memory devices H10BThis subclass covers devices or arrangements for storage of digital or analogue information:in which no relative movement takes place between an information storage element and a transducer;which incorporate a selecting-device for writing-in or reading-out the information into or from the store.This subclass does not cover elements not adapted for storage and not provided with such means as referred to in Note (3) below, which elements are classified in the appropriate subclass, e.g. of H01, H03K. In this subclass, the following terms are used with the meaning indicated: "storage element" is an element which can hold at least one item of information and is provided with means for writing-in or reading-out this information; "memory" is a device, including storage elements, which can hold information to be extracted when desired. The following IPC groups are not in the CPC scheme. The subject matter for these IPC groups is classified in the following CPC groups: G11C8/02 covered by G11C8/00, H03K17/00G11C11/4193 covered by G11C11/00G11C11/4195 covered by G11C11/00G11C11/4197 covered by G11C11/00In this subclass non-limiting references (in the sense of paragraph 39 of the Guide to the IPC) may still be displayed in the scheme. G11C5/00 G11C5/00Details of stores covered by group G11C11/00 G11C5/005Circuit means for protection against loss of information of semiconductor storage devices G11C5/02Disposition of storage elements, e.g. in the form of a matrix array G11C5/025Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207 G11C5/04Supports for storage elements , e.g. memory modulesMounting or fixing of storage elements on such supports G11C5/05Supporting of cores in matrix G11C5/06Arrangements for interconnecting storage elements electrically, e.g. by wiring G11C5/063Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay G11C5/066Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals G11C5/08for interconnecting magnetic elements, e.g. toroidal cores G11C5/10for interconnecting capacitors G11C5/12Apparatus or processes for interconnecting storage elements, e.g. for threading magnetic cores G11C5/14Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels G11C5/141Battery and back-up supplies G11C5/142Contactless power supplies, e.g. RF, induction, or IR G11C5/143Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence G11C5/144Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby G11C5/145Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence G11C5/146Substrate bias generators G11C5/141 takes precedence G11C5/147Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence G11C5/148Details of power up or power down circuits, standby circuits or recovery circuits G11C7/00Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413 G11C7/005with combined beam-and individual cell access G11C7/02with means for avoiding parasitic signals G11C7/04with means for avoiding disturbances due to temperature effects G11C7/06Sense amplifiersAssociated circuits , e.g. timing or triggering circuits G11C7/062Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs G11C7/065Differential amplifiers of latching type G11C7/067Single-ended amplifiers G11C7/08Control thereof G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers G11C7/1003Interface circuits for daisy chain or ring bus memory arrangements G11C7/1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor G11C7/1009Data masking during input/output G11C7/1012Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port G11C7/1018Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters G11C7/1021Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address G11C7/1024Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time G11C7/1027Static column decode serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled bit line addresses G11C7/103using serially addressed read-write data registers G11C7/1036 takes precedence G11C7/1033using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode G11C7/1036using data shift registers G11C7/1039using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers G11C7/1042using interleaving techniques, i.e. read-write of one part of the memory while preparing another part G11C7/1045Read-write mode select circuits G11C7/1048Data bus control circuits, e.g. precharging, presetting, equalising G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits G11C7/1054Optical output buffers G11C7/1057Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load G11C7/106Data output latches G11C7/1063Control signal output circuits, e.g. status or busy flags, feedback command signals G11C7/1066Output synchronization G11C7/1069I/O lines read out arrangements G11C7/1072for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories G11C7/1075for multiport memories each having random access ports and serial ports, e.g. video RAM G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits G11C7/1081Optical input buffers G11C7/1084Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load G11C7/1087Data input latches G11C7/109Control signal input circuits G11C7/1093Input synchronization G11C7/1096Write circuits, e.g. I/O line write drivers G11C7/12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines G11C7/14Dummy cell managementSense reference voltage generators G11C7/16Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters  G11C7/18Bit line organisationBit line lay-out G11C7/20Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory G11C7/22Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management  G11C7/222Clock generating, synchronizing or distributing circuits within memory device G11C7/225Clock input buffers G11C7/227Timing of memory operations based on dummy memory elements or replica circuits G11C7/24Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writingStatus cellsTest cells G11C8/00Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413 G11C8/005with travelling wave access G11C8/04using a sequential addressing device, e.g. shift register, counter G11C8/06Address interface arrangements, e.g. address buffers G11C8/08Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines G11C8/10Decoders G11C8/12Group selection circuits, e.g. for memory block selection, chip selection, array selection G11C8/14Word line organisationWord line lay-out G11C8/16Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups G11C8/18Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals G11C8/20Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor G11C14/00 - G11C21/00 take precedenceGroup G11C11/56 takes precedence over groups G11C11/02 - G11C11/54.
This Note corresponds to IPC Note (1) relating to G11C11/02 - G11C11/56. G11C11/005comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells G11C11/02using magnetic elements G11C11/04using storage elements having cylindrical form, e.g. rod, wire G11C11/12, G11C11/14 take precedence G11C11/06using single-aperture storage elements, e.g. ring coreusing multi-aperture plates in which each individual aperture forms a storage element G11C11/06007using a single aperture or single magnetic closed circuit Provisionally contains the following details; control write -, read -, address circuitry (pulse generators in general H03K5/00, H03K17/00 ); arrangements for temperature compensation; checking of the correct functioning and repair arrangements (checking methods in general G06F11/00, G06F11/28; testing magnetic elements per se G01R33/00 ); magnetic properties, choice of materials or the like (materials per se H01F1/00 ) G11C11/06014using one such element per bit G11C11/06021with destructive read-out G11C11/06028Matrixes G11C11/06035Bit core selection for writing or reading, by at least two coincident partial currents, e.g. "bit"- organised, 2L/2D, or 3D G11C11/06042"word"-organised, e.g. 2D organisation or linear selection, i.e. full current selection through all the bit-cores of a word during reading G11C11/0605with non-destructive read-out G11C11/06057Matrixes G11C11/06064"bit"-organised (2 1/2D, 3D or similar organisation) G11C11/06071"word"-organised (2D organisation or linear selection) G11C11/06078using two or more such elements per bit G11C11/06085Multi-aperture structures or multi-magnetic closed circuits, each aperture storing a "bit", realised by rods, plates, grids, waffle-irons,(i.e. grooved plates) or similar devices G11C11/06092Multi-aperture structures or multi-magnetic closed circuits using two or more apertures per bit G11C11/061using elements with single aperture or magnetic loop for storage, one element per bit, and for destructive read-out contains no documents, see G11C11/06007, G11C11/06014, G11C11/06021, G11C11/06028 G11C11/063bit organised, such as 2 1/2D, 3D organisation, i.e. for selection of an element by means of at least two coincident partial currents both for reading and for writing contains no documents; see G11C11/06035 G11C11/065word organised, such as 2D organisation, or linear selection, i.e. for selection of all the elements of a word by means of a single full current for reading contains no documents; see G11C11/06042 G11C11/067using elements with single aperture or magnetic loop for storage, one element per bit, and for non-destructive read-out contains no documents, see G11C11/0605 - G11C11/06071 G11C11/08using multi-aperture storage elements, e.g. using transfluxorsusing plates incorporating several individual multi-aperture storage elements G11C11/10 takes precedence G11C11/10using multi-axial storage elements G11C11/12using tensorsusing twistors, i.e. elements in which one axis of magnetisation is twisted G11C11/14using thin-film elements G11C11/15using multiple magnetic layers G11C11/155 takes precedence G11C11/155with cylindrical configuration G11C11/16using elements in which the storage effect is based on magnetic spin effect G11C11/161details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell G11C11/165Auxiliary circuits G11C11/1653Address circuits or decoders G11C11/1655Bit-line or column circuits G11C11/1657Word-line or row circuits G11C11/1659Cell access G11C11/1673Reading or sensing circuits or methods G11C11/1675Writing or programming circuits or methods G11C11/1677Verifying circuits or methods G11C11/1693Timing circuits or methods G11C11/1695Protection circuits or methods G11C11/1697Power supply circuits G11C11/18using Hall-effect devices G11C11/19using non-linear reactive devices in resonant circuits G11C11/20using parametrons G11C11/21using electric elements G11C11/22using ferroelectric elements G11C11/221using ferroelectric capacitors G11C11/223using MOS with ferroelectric gate insulating film G11C11/225Auxiliary circuits G11C11/2253Address circuits or decoders G11C11/2255Bit-line or column circuits G11C11/2257Word-line or row circuits G11C11/2259Cell access G11C11/2273Reading or sensing circuits or methods G11C11/2275Writing or programming circuits or methods G11C11/2277Verifying circuits or methods G11C11/2293Timing circuits or methods G11C11/2295Protection circuits or methods G11C11/2297Power supply circuits G11C11/23using electrostatic storage on a common layer, e.g. Forrester-Haeff tubes or William tubesG11C11/22 takes precedence G11C11/24using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40 G11C11/26using discharge tubes G11C11/265counting tubes, e.g. decatrons or trochotrons G11C11/28using gas-filled tubes G11C11/30using vacuum tubes G11C11/23 takes precedence G11C11/34using semiconductor devices G11C11/35with charge storage in a depletion layer, e.g. charge coupled devices G11C11/36using diodes, e.g. as threshold elements , i.e. diodes assuming a stable ON-stage when driven above their threshold (S- or N-characteristic) G11C11/38using tunnel diodes G11C11/39using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT G11C11/40using transistors G11C11/401forming cells needing refreshing or charge regeneration, i.e. dynamic cells G11C11/402with charge regeneration individual to each memory cell, i.e. internal refresh G11C11/4023using field effect transistors G11C11/4026using bipolar transistors G11C11/403with charge regeneration common to a multiplicity of memory cells, i.e. external refresh G11C11/404with one charge-transfer gate, e.g. MOS transistor, per cell G11C11/4045using a plurality of serially connected access transistors, each having a storage capacitor G11C11/405with three charge-transfer gates, e.g. MOS transistors, per cell G11C11/406Management or control of the refreshing or charge-regeneration cycles G11C11/40603Arbitration, priority and concurrent access to memory cells for read/write or refresh operations G11C11/40607Refresh operations in memory devices with an internal cache or data buffer G11C11/40611External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh G11C11/40615Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs G11C11/40618Refresh operations over multiple banks or interleaving G11C11/40622Partial refresh of memory arrays G11C11/40626Temperature related aspects of refresh operations G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing G11C11/4067for memory cells of the bipolar type G11C11/407for memory cells of the field-effect type G11C11/4072Circuits for initialization, powering up or down, clearing memory or presetting G11C11/4074Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits G11C11/4076Timing circuits for regeneration management G11C11/406 G11C11/4078Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writingStatus cellsTest cells protection of memory contents during checking or testing G11C29/52 G11C11/408Address circuits G11C11/4082Address Buffers; level conversion circuits G11C11/4085Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge G11C11/4087Address decoders, e.g. bit - or word line decoders; Multiple line decoders G11C11/409Read-write [R-W] circuits  G11C11/4091Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating G11C11/4093Input/output [I/O] data interface arrangements, e.g. data buffers G11C11/4094Bit-line management or control circuits G11C11/4096Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches  G11C11/4097Bit-line organisation, e.g. bit-line layout, folded bit lines G11C11/4099Dummy cell treatmentReference voltage generators G11C11/41forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger G11C11/411using bipolar transistors only G11C11/4113with at least one cell access to base or collector of at least one of said transistors, e.g. via access diodes, access transistors G11C11/4116with at least one cell access via separately connected emittors of said transistors or via multiple emittors, e.g. T2L, ECL G11C11/412using field-effect transistors only G11C11/4125Cells incorporating circuit means for protecting against loss of information G11C11/413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction G11C11/414for memory cells of the bipolar type G11C11/415Address circuits G11C11/416Read-write [R-W] circuits  G11C11/417for memory cells of the field-effect type G11C11/418Address circuits G11C11/419Read-write [R-W] circuits G11C11/42using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically- coupled or feedback-coupled G11C11/44using super-conductive elements, e.g. cryotron G11C11/46using thermoplastic elements G11C11/48using displaceable coupling elements, e.g. ferromagnetic cores, to produce change between different states of mutual or self-inductance contains no documents; see G11C17/00 and subgroups G11C11/50using actuation of electric contacts to store the information G11C11/52using electromagnetic relays G11C11/54using elements simulating biological cells, e.g. neuron G11C11/56using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency G11C11/5607using magnetic storage elements G11C11/5614using conductive bridging RAM [CBRAM] or programming metallization cells [PMC] G11C11/5621using charge storage in a floating gate G11C11/5628Programming or writing circuits; Data input circuits G11C11/5635Erasing circuits G11C11/5642Sensing or reading circuits; Data output circuits G11C11/565using capacitive charge storage elements G11C11/5657using ferroelectric storage elements G11C11/5664using organic memory material storage elements G11C11/5671using charge trapping in an insulator G11C11/5678using amorphous/crystalline phase transition storage elements G11C11/5685using storage elements comprising metal oxide memory material, e.g. perovskites G11C11/5692read-only digital stores using storage elements with more than two stable states G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 G11C13/0002using resistive RAM [RRAM] elements G11C13/0004comprising amorphous/crystalline phase transition cells G11C13/0007comprising metal oxide memory material, e.g. perovskites G11C13/0009RRAM elements whose operation depends upon chemical change G11C13/0011comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs] G11C13/0014comprising cells based on organic memory material G11C13/0016comprising polymers G11C13/0019comprising bio-molecules G11C13/0021Auxiliary circuits G11C13/0023Address circuits or decoders G11C13/0026Bit-line or column circuits G11C13/0028Word-line or row circuits G11C13/003Cell access G11C13/0033Disturbance prevention or evaluation; Refreshing of disturbed memory data G11C13/0035Evaluating degradation, retention or wearout, e.g. by counting writing cycles G11C13/0038Power supply circuits G11C13/004Reading or sensing circuits or methods G11C2013/0042Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB] G11C2013/0045Read using current through the cell G11C2013/0047Read destroying or disturbing the data G11C2013/005Read using potential difference applied between cell electrodes G11C2013/0052Read process characterized by the shape, e.g. form, length, amplitude of the read pulse G11C2013/0054Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell G11C2013/0057Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value G11C13/0059Security or protection circuits or methods G11C13/0061Timing circuits or methods G11C13/0064Verifying circuits or methods G11C2013/0066Verify correct writing whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing G11C13/0069Writing or programming circuits or methods G11C2013/0071Write using write potential applied to access device gate G11C2013/0073Write using bi-directional cell biasing G11C2013/0076Write operation performed depending on read result G11C2013/0078Write using current through the cell G11C2013/008Write by generating heat in the surroundings of the memory material, e.g. thermowrite G11C2013/0083Write to perform initialising, forming process, electro forming or conditioning G11C2013/0085Write a page or sector of information simultaneously, e.g. a complete row or word line G11C2013/0088Write with the simultaneous writing of a plurality of cells G11C2013/009Write using potential difference applied between cell electrodes G11C2013/0092Write characterized by the shape, e.g. form, length, amplitude of the write pulse G11C2013/0095Write using strain induced by, e.g. piezoelectric, thermal effects G11C13/0097Erasing, e.g. resetting, circuits or methods G11C13/02using elements whose operation depends upon chemical change G11C13/0009 takes precedence G11C13/025using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes G11C13/04using optical elements ; using other beam accessed elements, e.g. electron or ion beam G11C13/041using photochromic storage elements G11C13/042 takes precedence G11C13/042using information stored in the form of interference pattern G11C13/043using magnetic-optical storage elements G11C13/044using electro-optical elements G11C13/045using photochromic storage elements G11C13/046using other storage elements storing information in the form of an interference pattern G11C13/047using electro-optical elements G11C13/042 takes precedence G11C13/048using other optical storage elements G11C13/06using magneto-optical elements G11C13/042 takes precedence G11C14/00Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down G11C14/0009in which the volatile element is a DRAM cell G11C14/0018whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor G11C14/0027and the nonvolatile element is a ferroelectric element G11C14/0036and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell G11C14/0045and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material G11C14/0054in which the volatile element is a SRAM cell G11C14/0063and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor G11C14/0072and the nonvolatile element is a ferroelectric element G11C14/0081and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell G11C14/009and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material G11C15/00Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores G11C15/02using magnetic elements G11C15/04using semiconductor elements G11C15/043using capacitive charge storage elements G11C15/046using non-volatile storage elements G11C15/06using cryogenic elements G11C16/00Erasable programmable read-only memories G11C14/00 takes precedence G11C16/02electrically programmable G11C16/04using variable threshold transistors, e.g. FAMOS G11C16/0408comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence G11C16/0416comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM G11C16/0425comprising cells containing a merged floating gate and select transistor G11C16/0433comprising cells containing a single floating gate transistor and one or more separate select transistors G11C16/0441comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates G11C16/045Floating gate memory cells with both P and N channel memory transistors, usually sharing a common floating gate G11C16/0458comprising two or more independent floating gates which store independent data G11C16/0466comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence G11C16/0475comprising two or more independent storage sites which store independent data G11C16/0483comprising cells having several storage transistors connected in series G11C16/0491Virtual ground arrays G11C16/06Auxiliary circuits, e.g. for writing into memory G11C16/08Address circuitsDecodersWord-line control circuits G11C16/10Programming or data input circuits G11C16/102External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators G11C16/105Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written G11C16/107Programming all cells in an array, sector or block to the same state prior to flash erasing G11C16/12Programming voltage switching circuits G11C16/14Circuits for erasing electrically, e.g. erase voltage switching circuits G11C16/16for erasing blocks, e.g. arrays, words, groups G11C16/18Circuits for erasing optically G11C16/20InitialisingData presetChip identification G11C16/22Safety or protection circuits preventing unauthorised or accidental access to memory cells G11C16/225Preventing erasure, programming or reading when power supply voltages are outside the required ranges G11C16/24Bit-line control circuits G11C16/26Sensing or reading circuitsData output circuits G11C16/28using differential sensing or reference cells, e.g. dummy cells G11C16/30Power supply circuits G11C16/32Timing circuits G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention G11C16/3404Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells G11C16/3409Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step G11C16/3413Circuits or methods to recover overprogrammed nonvolatile memory cells detected during program verification, usually by means of a "soft" erasing step G11C16/3418Disturbance prevention or evaluation; Refreshing of disturbed memory data G11C16/3422Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem G11C16/3427Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written G11C16/3431Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step G11C16/3436Arrangements for verifying correct programming or erasure G11C16/344Arrangements for verifying correct erasure or for detecting overerased cells G11C16/3445Circuits or methods to verify correct erasure of nonvolatile memory cells G11C16/345Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification G11C16/3454Arrangements for verifying correct programming or for detecting overprogrammed cells G11C16/3459Circuits or methods to verify correct programming of nonvolatile memory cells G11C16/3463Circuits or methods to detect overprogrammed nonvolatile memory cells, usually during program verification G11C16/3468Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing G11C16/3472Circuits or methods to verify correct erasure of nonvolatile memory cells whilst erasing is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasure G11C16/3477Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing G11C16/3481Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming G11C16/3486Circuits or methods to prevent overprogramming of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming G11C16/349Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles G11C16/3495Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically G11C17/00Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards G11C17/005with a storage element common to a large number of data, e.g. perforated card G11C17/02, G11C17/04 take precedence G11C17/02using magnetic or inductive elements G11C17/14 takes precedence G11C17/04using capacitive elements G11C17/06, G11C17/14 take precedence G11C17/06using diode elements G11C17/14 takes precedence G11C17/08using semiconductor devices, e.g. bipolar elements G11C17/06, G11C17/14 take precedence G11C17/10in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM G11C17/12using field-effect devices G11C17/123comprising cells having several storage transistors connected in series G11C17/126Virtual ground arrays G11C17/14in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM G11C17/143using laser-fusible links G11C17/146Write once memory, i.e. allowing changing of memory content by writing additional bits G11C17/16using electrically-fusible links G11C17/165Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002 G11C17/18Auxiliary circuits, e.g. for writing into memory G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers G11C19/005with ferro-electric elements (condensers) G11C19/02using magnetic elements G11C19/14 takes precedence G11C19/04using cores with one aperture or magnetic loop G11C19/06using structures with a number of apertures or magnetic loops, e.g. transfluxors laddic G11C19/08using thin films in plane structure G11C19/0808using magnetic domain propagation G11C19/0816using a rotating or alternating coplanar magnetic field G11C19/0825using a variable perpendicular magnetic field G11C19/0833using magnetic domain interaction G11C19/0841using electric current G11C19/085Generating magnetic fields therefor, e.g. uniform magnetic field for magnetic domain stabilisation G11C19/0858Generating, replicating or annihilating magnetic domains (also comprising different types of magnetic domains, e.g. "Hard Bubbles") G11C19/0866 takes precedence G11C19/0866Detecting magnetic domains G11C19/0875Organisation of a plurality of magnetic shift registers G11C19/0883Means for switching magnetic domains from one path into another path, i.e. transfer switches, swap gates or decoders G11C19/0891using hybrid structure, e.g. ion doped layers G11C19/10using thin films on rodswith twistors G11C19/12using non-linear reactive devices in resonant circuits , e.g. parametrons; magnetic amplifiers with overcritical feedback G11C19/14using magnetic elements in combination with active elements, e.g. discharge tubes, semiconductor elements contains no documents, see provisionally G11C19/02 - G11C19/10 G11C19/18using capacitors as main elements of the stages if capacitors are used as auxiliary stage in between main stages with other elements, the latter take precedence; G11C19/005 takes precedence G11C19/182in combination with semiconductor elements, e.g. bipolar transistors, diodes G11C19/184with field-effect transistors, e.g. MOS-FET G11C19/186using only one transistor per capacitor, e.g. bucket brigade shift register G11C19/188Organisation of a multiplicity of shift registers, e.g. regeneration, timing or input-output circuits G11C19/20using discharge tubes G11C19/14 takes precedence G11C19/202with vacuum tubes G11C19/207 takes precedence G11C19/205with gas-filled tubes G11C19/207 takes precedence G11C19/207with counting tubes G11C19/28using semiconductor elements G11C19/14, G11C19/36 take precedence G11C19/282with charge storage in a depletion layer, i.e. charge coupled devices [CCD] G11C19/285Peripheral circuits, e.g. for writing into the first stage; for reading-out of the last stage G11C19/287Organisation of a multiplicity of shift registers G11C19/30using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled G11C19/32using super-conductive elements G11C19/34using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency G11C19/36using multistable semiconductor elements G11C19/38two-dimensional, e.g. horizontal and vertical shift registers G11C21/00Digital stores in which the information circulates continuouslystepwise G11C19/00 G11C21/005using electrical delay lines G11C21/02using electromechanical delay lines, e.g. using a mercury tank G11C21/023using piezo-electric transducers, e.g. mercury tank G11C21/026using magnetostriction transducers, e.g. nickel delay line G11C23/00Digital stores characterised by movement of mechanical parts to effect storage, e.g. using ballsStorage elements therefor G11C25/00Digital stores characterised by the use of flowing mediaStorage elements therefor G11C27/00Electric analogue stores, e.g. for storing instantaneous values G11C27/005with non-volatile charge storage, e.g. on floating gate or MNOS G11C27/02Sample-and-hold arrangements G11C27/04 takes precedence G11C27/022using a magnetic memory element G11C27/024using a capacitive memory element G11C27/04 takes precedence G11C27/026associated with an amplifier G11C27/028 takes precedence G11C27/028Current mode circuits, e.g. switched current memories G11C27/04Shift registers G11C29/00Checking stores for correct operation ; Subsequent repairTesting stores during standby or offline operation G11C29/003in serial memories G11C29/006at wafer scale level, i.e. wafer scale integration [WSI] G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters G11C29/021in voltage or current generators G11C29/022in I/O circuitry G11C29/023in clock generator or timing circuitry G11C29/024in decoders G11C29/025in signal lines G11C29/026in sense amplifiers G11C29/027in fuses G11C29/028with adaption or trimming of parameters G11C29/04Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals G11C2029/0401in embedded memories G11C2029/0403during or with feedback to manufacture G11C2029/0405comprising complete test loop G11C2029/0407on power on G11C2029/0409Online test G11C2029/0411Online error correction G11C29/06Acceleration testing G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing G11C29/10Test algorithms, e.g. memory scan [MScan] algorithmsTest patterns, e.g. checkerboard patterns  G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details G11C29/12005comprising voltage or current generators G11C29/1201comprising I/O circuitry G11C29/12015comprising clock generation or timing circuitry G11C2029/1202Word line control G11C2029/1204Bit line control G11C2029/1206Location of test circuitry on chip or wafer G11C2029/1208Error catch memory G11C29/14Implementation of control logic, e.g. test mode decoders G11C29/16using microprogrammed units, e.g. state machines G11C29/18Address generation devicesDevices for accessing memories, e.g. details of addressing circuits G11C2029/1802Address decoder G11C2029/1804Manipulation of word size G11C2029/1806Address conversion or mapping, i.e. logical to physical address G11C29/20using counters or linear-feedback shift registers [LFSR] G11C29/22Accessing serial memories G11C29/24Accessing extra cells, e.g. dummy cells or redundant cells G11C29/26Accessing multiple arrays G11C29/24 takes precedence G11C2029/2602Concurrent test G11C29/28Dependent multiple arrays, e.g. multi-bit arrays G11C29/30Accessing single arrays G11C29/32Serial accessScan testing G11C2029/3202Scan chain G11C29/34Accessing multiple bits simultaneously G11C29/36Data generation devices, e.g. data inverters G11C2029/3602Pattern generator G11C29/38Response verification devices G11C29/40using compression techniques G11C2029/4002Comparison of products, i.e. test results of chips or with golden chip G11C29/42using error correcting codes [ECC] or parity check G11C29/44Indication or identification of errors, e.g. for repair G11C29/4401for self repair G11C2029/4402Internal storage of test result, quality data, chip identification, repair information G11C29/46Test trigger logic G11C29/48Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths G11C29/50Marginal testing, e.g. race, voltage or current testing G11C29/50004of threshold voltage G11C29/50008of impedance G11C29/50012of timing G11C29/50016of retention G11C2029/5002Characteristic G11C2029/5004Voltage G11C2029/5006Current G11C29/52Protection of memory contentsDetection of errors in memory contents G11C29/54Arrangements for designing test circuits, e.g. design for test [DFT] tools G11C29/56External testing equipment for static stores, e.g. automatic test equipment [ATE]Interfaces therefor G11C29/56004Pattern generation G11C29/56008Error analysis, representation of errors G11C29/56012Timing aspects, clock generation, synchronisation G11C29/56016Apparatus features G11C2029/5602Interface to device under test G11C2029/5604Display of error information G11C2029/5606Error catch memory G11C29/70Masking faults in memories by using spares or by reconfiguring G11C29/702by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones G11C29/72with optimized replacement algorithms G11C29/74using duplex memories, i.e. using dual copies G11C29/76using address translation or modifications G11C29/765in solid state disks G11C29/78using programmable devices G11C29/781combined in a redundant decoder G11C29/783with refresh of replacement cells, e.g. in DRAMs G11C29/785with redundancy programming schemes G11C29/787using a fuse hierarchy G11C29/789using non-volatile cells or latches G11C29/80with improved layout G11C29/802by encoding redundancy signals G11C29/804to prevent clustered faults G11C29/806by reducing size of decoders G11C29/808using a flexible replacement scheme G11C29/81using a hierarchical redundancy scheme G11C29/812using a reduced amount of fuses G11C29/814for optimized yield G11C29/816for an application-specific layout G11C29/818for dual-port memories G11C29/82for EEPROMs G11C29/822for read only memories G11C29/824for synchronous memories G11C29/83with reduced power consumption G11C29/832with disconnection of faulty elements G11C29/835with roll call arrangements for redundant substitutions G11C29/838with substitution of defective spares G11C29/84with improved access time or stability G11C29/842by introducing a delay in a signal path G11C29/844by splitting the decoders in stages G11C29/846by choosing redundant lines at an output stage G11C29/848by adjacent switching G11C29/86in serial access memories, e.g. shift registers, CCDs, bubble memories G11C29/88with partially good memories G11C29/883using a single defective memory device with reduced capacity, e.g. half capacity G11C29/886combining plural defective memory devices to provide a contiguous address range, e.g. one device supplies working blocks to replace defective blocks in another device G11C99/00Subject matter not provided for in other groups of this subclass G11C2207/00 G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store G11C2207/002Isolation gates, i.e. gates coupling bit lines to the sense amplifier G11C2207/005Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines G11C2207/007Register arrays G11C2207/06Sense amplifier related aspects G11C2207/061Sense amplifier enabled by a address transition detection related control signal G11C2207/063Current sense amplifiers G11C2207/065Sense amplifier drivers G11C2207/066Frequency reading type sense amplifier G11C2207/068Integrator type sense amplifier G11C2207/10Aspects relating to interfaces of memory device to external buses G11C2207/101Analog or multilevel bus G11C2207/102Compression or decompression of data before storage G11C2207/104Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs G11C2207/105Aspects related to pads, pins or terminals G11C2207/107Serial-parallel conversion of data or prefetch G11C2207/108Wide data ports G11C2207/12Equalization of bit lines G11C2207/16Solid state audio deprecated, only for historical reasons, G06F3/16, G11B G11C2207/22Control and timing of internal memory operations G11C2207/2209Concurrent read and write for multi-port memory G11C7/1075 G11C2207/2218Late write G11C2207/2227Standby or low power modes G11C2207/2236Copy G11C2207/2245Memory devices with an internal cache buffer G11C2207/2254Calibration G11C2207/2263Write conditionally, e.g. only if new data and old data differ G11C2207/2272Latency related aspects G11C2207/2281Timing of a read operation sense amplifier timing G11C7/06, G11C7/08 G11C2207/229Timing of a write operation sense amplifier timing G11C7/06, G11C7/08 G11C2211/00Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elementsStorage elements therefor G11C2211/401Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells G11C2211/4013Memory devices with multiple cells per bit, e.g. twin-cells G11C2211/4016Memory devices with silicon-on-insulator cells G11C2211/406Refreshing of dynamic cells G11C2211/4061Calibration or ate or cycle tuning G11C2211/4062Parity or ECC in refresh operations G11C2211/4063Interleaved refresh operations G11C2211/4065Low level details of refresh operations G11C2211/4066Pseudo-SRAMs G11C2211/4067Refresh in standby or low power modes G11C2211/4068Voltage or leakage in refresh operations G11C2211/56Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups G11C2211/561Multilevel memory cell aspects G11C2211/5611Multilevel memory cell with more than one control gate G11C2211/5612Multilevel memory cell with more than one floating gate G11C2211/5613Multilevel memory cell with additional gates, not being floating or control gates G11C2211/5614Multilevel memory cell comprising negative resistance, quantum tunneling or resonance tunneling elements G11C2211/5615Multilevel magnetic memory cell using non-magnetic non-conducting interlayer, e.g. MTJ G11C2211/5616Multilevel magnetic memory cell using non-magnetic conducting interlayer, e.g. GMR, SV, PSV G11C2211/5617Multilevel ROM cell programmed by source, drain or gate contacting G11C2211/562Multilevel memory programming aspects G11C2211/5621Multilevel programming verification G11C2211/5622Concurrent multilevel programming of more than one cell G11C2211/5623Concurrent multilevel programming and reading G11C2211/5624Concurrent multilevel programming and programming verification G11C2211/5625Self-converging multilevel programming G11C2211/563Multilevel memory reading aspects G11C2211/5631Concurrent multilevel reading of more than one cell G11C2211/5632Multilevel reading using successive approximation G11C2211/5633Mixed concurrent serial multilevel reading G11C2211/5634Reference cells G11C2211/564Miscellaneous aspects G11C2211/5641Multilevel memory having cells with different number of storage levels G11C2211/5642Multilevel memory with buffers, latches, registers at input or output G11C2211/5643Multilevel memory comprising cache storage devices G11C2211/5644Multilevel memory comprising counting devices G11C2211/5645Multilevel memory with current-mirror arrangements G11C2211/5646Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page" G11C2211/5647Multilevel memory with bit inversion arrangement G11C2211/5648Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant G11C2211/5649Multilevel memory with plate line or layer, e.g. in order to lower programming voltages G11C2211/565Multilevel memory comprising elements in triple well structure G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group G11C2213/10Resistive cellsTechnology aspects G11C2213/11Metal ion trapping, i.e. using memory material including cavities, pores or spaces in form of tunnels or channels wherein metal ions can be trapped but do not react and form an electro-deposit creating filaments or dendrites G11C2213/12Non-metal ion trapping, i.e. using memory material trapping non-metal ions given by the electrode or another layer during a write operation, e.g. trapping, doping G11C2213/13Dissociation, i.e. using memory material including molecules which, during a write operation, are dissociated in ions which migrate further in the memory material G11C2213/14Use of different molecule structures as storage states, e.g. part of molecule being rotated G11C2213/15Current-voltage curve G11C2213/16Memory cell being a nanotube, e.g. suspended nanotube G11C2213/17Memory cell being a nanowire transistor G11C2213/18Memory cell being a nanowire having RADIAL composition G11C2213/19Memory cell comprising at least a nanowire and only two terminals G11C2213/30Resistive cell, memory material aspects G11C2213/31Material having complex metal oxide, e.g. perovskite structure G11C2213/32Material having simple binary metal oxide structure G11C2213/33Material including silicon G11C2213/34Material includes an oxide or a nitride G11C2213/35Material including carbon, e.g. graphite, grapheme G11C2213/50Resistive cell structure aspects G11C2213/51Structure including a barrier layer preventing or limiting migration, diffusion of ions or charges or formation of electrolytes near an electrode G11C2213/52Structure characterized by the electrode material, shape, etc. G11C2213/53Structure wherein the resistive material being in a transistor, e.g. gate G11C2213/54Structure including a tunneling barrier layer, the memory effect implying the modification of tunnel barrier conductivity G11C2213/55Structure including two electrodes, a memory active layer and at least two other layers which can be a passive or source or reservoir layer or a less doped memory active layer G11C2213/56Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way G11C2213/70Resistive array aspects G11C2213/71Three dimensional array G11C2213/72Array wherein the access device being a diode G11C2213/73Array where access device function, e.g. diode function, being merged with memorizing function of memory element G11C2213/74Array wherein each memory cell has more than one access device G11C2213/75Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor G11C2213/76Array using an access device for each cell which being not a transistor and not a diode G11C2213/77Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used G11C2213/78Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver G11C2213/79Array wherein the access device being a transistor G11C2213/80Array wherein the substrate, the cell, the conductors and the access device are all made up of organic materials G11C2213/81Array wherein the array conductors, e.g. word lines, bit lines, are made of nanowires G11C2213/82Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials G11C2216/00Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups G11C2216/02Structural aspects of erasable programmable read-only memories G11C2216/04Nonvolatile memory cell provided with a separate control gate for erasing the cells, i.e. erase gate, independent of the normal read control gate G11C2216/06Floating gate cells in which the floating gate consists of multiple isolated silicon islands, e.g. nanocrystals G11C2216/08Nonvolatile memory wherein data storage is accomplished by storing relatively few electrons in the storage layer, i.e. single electron memory G11C2216/10Floating gate memory cells with a single polysilicon layer G11C2216/12Reading and writing aspects of erasable programmable read-only memories G11C2216/14Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory G11C2216/16Flash programming of all the cells in an array, sector or block simultaneously G11C2216/18Flash erasure of all the cells in an array, sector or block simultaneously G11C2216/20Suspension of programming or erasing cells in an array in order to read other cells in it G11C2216/22Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously G11C2216/24Nonvolatile memory in which programming can be carried out in one memory bank or array whilst a word or sector in another bank or array is being erased simultaneously G11C2216/26Floating gate memory which is adapted to be one-time programmable [OTP], e.g. containing multiple OTP blocks permitting limited update ability G11C2216/28Floating gate memory programmed by reverse programming, e.g. programmed with negative gate voltage and erased with positive gate voltage or programmed with high source or drain voltage and erased with high gate voltage G11C2216/30Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory G11C2229/00Indexing scheme relating to checking stores for correct operation, subsequent repair or testing stores during standby or offline operation G11C2229/70Indexing scheme relating to G11C29/70, for implementation aspects of redundancy repair G11C2229/72Location of redundancy information G11C2229/723Redundancy information stored in a part of the memory core to be repaired G11C2229/726Redundancy information loaded from the outside into the memory G11C2229/74Time at which the repair is done G11C2229/743After packaging G11C2229/746Before packaging G11C2229/76Storage technology used for the repair G11C2229/763E-fuses, e.g. electric fuses or antifuses, floating gate transistors G11C2229/766Laser fuses