H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES of dynamo-electric generators H02PThis subclass covers: automatic control circuits for generators of electronic oscillations or pulses; starting, synchronisation, or stabilisation circuits for generators where the type of generator is irrelevant or unspecified.This subclass does not cover stabilisation or starting circuits specially adapted to only one specific type of generator, which are covered by subclasses H03B, H03K.In this subclass, the following expression is used with the meaning indicated: "automatic control" covers only closed loop systems.In this subclass non-limiting references (in the sense of paragraph 39 of the Guide to the IPC) may still be displayed in the scheme. H03L1/00 H03L1/00Stabilisation of generator output against variations of physical values, e.g. power supply automatic control H03L5/00, H03L7/00 H03L1/02against variations of temperature only H03L1/021of generators comprising distributed capacitance and inductance H03L1/022by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature H03L1/021 takes precedence H03L1/023by using voltage variable capacitance diodes H03L1/025and a memory for digitally storing correction values H03L1/026by using a memory for digitally storing correction values H03L1/025 takes precedence H03L1/027by using frequency conversion means which is variable with temperature, e.g. mixer, frequency divider, pulse add/substract logic circuit H03L1/023, H03L1/026 take precedence H03L1/028of generators comprising piezo-electric resonators H03L1/021 and H03L1/022 take precedence; oscillation generators with a piezo-electric resonator per se H03B5/32 H03L1/04Constructional details for maintaining temperature constant H03L3/00Starting of generators H03L5/00Automatic control of voltage, current, or power H03L5/02of power H03L7/00Automatic control of frequency or phaseSynchronisation tuning of resonant circuits in general H03J; synchronising in digital communication systems, see the relevant groups in class H04 H03L7/02using a frequency discriminator comprising a passive frequency-determining element H03L7/04wherein the frequency-determining element comprises distributed inductance and capacitance H03L7/06using a reference signal applied to a frequency- or phase-locked loop H03L7/07using several loops, e.g. for redundant clock signal generation for indirect frequency synthesis H03L7/22 H03L7/08Details of the phase-locked loop H03L7/0802the loop being adapted for reducing power consumption H03L7/14 takes precedence H03L7/0805the loop being adapted to provide an additional control signal for use outside the loop H03L7/0807concerning mainly a recovery circuit for the reference signal H03L7/081provided with an additional controlled phase shifter H03L7/0998 takes precedence H03L7/0812and where no voltage or current controlled oscillator is used H03L7/0814the phase shifting device being digitally controlled H03L7/0816the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input H03L7/0818the controlled phase shifter comprising coarse and fine delay or phase-shifting means H03L7/083the reference signal being additionally directly applied to the generator direct frequency synchronisation without loop H03L7/24 H03L7/085concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; frequency or phase detection comparison in general H03D3/00, H03D13/00 H03L7/087using at least two phase detectors or a frequency and phase detector in the loop H03L7/089the phase or frequency detector generating up-down pulses H03L7/087 takes precedence H03L7/0891the up-down pulses controlling source and sink current generators, e.g. a charge pump H03L7/0893the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop H03L7/0895Details of the current generators H03L7/0893 takes precedence H03L7/0896the current generators being controlled by differential up-down pulses H03L7/0898the source or sink current values being variable H03L7/0896 takes precedence H03L7/091the phase or frequency detector using a sampling device H03L7/087 takes precedence H03L7/093using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence H03L7/095using a lock detector H03L7/087 takes precedence H03L7/097using a comparator for comparing the voltages obtained from two frequency to voltage converters H03L7/099concerning mainly the controlled oscillator of the loop H03L7/0991the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814 H03L7/0992comprising a counter or a frequency divider H03L7/0993and a circuit for adding and deleting pulses H03L7/0994comprising an accumulator H03L7/0995the oscillator comprising a ring oscillator H03L7/0996Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator H03L7/0997Controlling the number of delay elements connected in series in the ring oscillator H03L7/0998using phase interpolation H03L7/10for assuring initial synchronisation or for broadening the capture range H03L7/101using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop H03L7/113, H03L7/187 take precedence H03L7/102the additional signal being directly applied to the controlled loop oscillator H03L7/103the additional signal being a digital signal H03L7/104using an additional signal from outside the loop for setting or controlling a parameter in the loop H03L7/107, H03L7/12 take precedence H03L7/105Resetting the controlled oscillator when its frequency is outside a predetermined limit H03L7/107using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth H03L7/1072by changing characteristics of the charge pump, e.g. changing the gain H03L7/1075by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth H03L7/1072 takes precedence H03L7/1077by changing characteristics of the phase or frequency detection means H03L7/1072 takes precedence H03L7/113using frequency discriminator H03L7/12using a scanning signal tuning circuits with automatic scanning over a band of frequencies H03J7/18 H03L7/14for assuring constant frequency when supply or correction voltages fail or are interrupted H03L7/141the phase-locked loop controlling several oscillators in turn H03L7/143by switching the reference signal of the phase-locked loop H03L7/145the switched reference signal being derived from the controlled oscillator output signal H03L7/146by using digital means for generating the oscillator control signal H03L7/141, H03L7/143 take precedence H03L7/148said digital means comprising a counter or a divider H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop H03L7/18using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence H03L7/1803the counter or frequency divider being connected to a cycle or pulse swallowing circuit H03L7/1806the frequency divider comprising a phase accumulator generating the frequency divided signal H03L7/181a numerical count result being used for locking the loop, the counter counting during fixed time intervals H03L7/1806 takes precedence H03L7/183a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence H03L7/185using a mixer in the loop H03L7/187 - H03L7/195 take precedence H03L7/187using means for coarse tuning the voltage controlled oscillator of the loop H03L7/191 - H03L7/195 take precedence H03L7/189comprising a D/A converter for generating a coarse tuning voltage H03L7/191using at least two different signals from the frequency divider or the counter for determining the time difference H03L7/193, H03L7/195 take precedence H03L7/193the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider pulse counters/frequency dividers H03K21/00 - H03K29/00 H03L7/195in which the counter of the loop counts between two different non zero numbers, e.g. for generating an offset frequency H03L7/193 takes precedence; pulse counters for predetermined counting H03K21/00 - H03K29/00 H03L7/197a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division H03L7/1806 takes precedence H03L7/1972for reducing the locking time interval H03L7/1974, H03L7/199 take precedence H03L7/1974for fractional frequency division H03L7/1976using a phase accumulator for controlling the counter or frequency divider H03L7/1978using a cycle or pulse removing circuit H03L7/199with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation H03L7/20using a harmonic phase-locked loop, i.e. a loop which can be locked to one of a number of harmonically related frequencies applied to it H03L7/22 takes precedence H03L7/22using more than one loop H03L7/23with pulse counters or frequency dividers H03L7/235Nested phase locked loops H03L7/24using a reference signal directly applied to the generator H03L7/26using energy levels of molecules, atoms, or subatomic particles as a frequency reference H03L9/00Automatic control not provided for in other groups of this subclass H03L2207/00 H03L2207/00Indexing scheme relating to automatic control of frequency or phase and to synchronisation H03L2207/04Modifications for maintaining constant the phase-locked loop damping factor when other loop parameters change H03L2207/05Compensating for non-linear characteristics of the controlled oscillator H03L2207/06Phase locked loops with a controlled oscillator having at least two frequency control terminals H03L2207/08Modifications of the phase-locked loop for ensuring constant frequency when the power supply fails or is interrupted, e.g. for saving power H03L2207/10Indirect frequency synthesis using a frequency multiplier in the phase-locked loop or in the reference signal path H03L2207/12Indirect frequency synthesis using a mixer in the phase-locked loop H03L2207/14Preventing false-lock or pseudo-lock of the PLL H03L2207/18Temporarily disabling, deactivating or stopping the frequency counter or divider H03L2207/50All digital phase-locked loop